This is the Online Practice Quiz in DC Biasing – FETs Part 6 from the book, Electronic Devices and Circuit Theory 10th Edition by Robert L. Boylestad. If you are looking for a reviewer in Electronics Engineering this will definitely help. I can assure you that this will be a great help in reviewing the book in preparation for your Board Exam. Make sure to familiarize each and every questions to increase the chance of passing the ECE Board Exam.
Continue Part VI of the Online Practice Quiz
Quiz in DC Biasing – FETs
Question 51. In a fixed-bias configuration, the voltage level of VGS is equal to _____.
Question 52. The dc load line is drawn using the equation obtained by applying Kirchhoff's voltage law (KVL) at _____ side loop(s) of the circuit.
Question 53. For R2 smaller than _____ kΩ the voltage VD is equal to VDD = 16 V.

Question 54. The slope of the dc load line in a self-bias configuration is controlled by _____.
Question 55. The controlled variable on the output side of an FET transistor is a _____ level.
Question 56. In a feedback-bias configuration, the slope of the dc load line is controlled by _____.
Question 57. In p-channel FETs, the level of VGS is _____ while the level of VDS is _____.
Question 58. The level of VDS is typically between _____ % and _____ % of VDD.
Question 59. In a universal JFET bias curve, the vertical scale labeled m is used to find the solution to the _____ configuration.
Question 60. The slope of the dc load line in a voltage-divider is controlled by _____.

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More Practice Quiz in DC Biasing – FETs
Practice Quiz Part 1
Practice Quiz Part 2
Practice Quiz Part 3
Practice Quiz Part 4
Practice Quiz Part 5
Practice Quiz Part 6
See: Complete List of Practice Quizzes
Note: After taking this particular quiz, you can proceed to check all the topics.
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